Equivalence checking is a form of static verification that employs formal, mathematical techniques to prove that two versions of a circuit design are, or are not, functionally equivalent. Thus, in circuit design typically once a design has undergone significant transformations equivalence checking tools are employed to verify that the new design is functionally equivalent to the previous design. Through equivalence checking the verification of the circuitry changes in the implementation phase of logic optimization, technology mapping, and place and route, are each handled. One of the shortcomings of equivalence checking tools is the production of a non-equivalent result when the designs are indeed equivalent, this may be referred to as a false-difference. Typically, a user's hints and settings are often required to guide an equivalence checking tool to the correct result. In addition, too many instances of registered duplication and reduction may become frustrating to users to the point where it is inefficient to use an equivalence checking tool.
It is in this context that the embodiments arise.